Contact hole production is a common step in semiconductor device manufacturing. The contact holes are typically used to make electrical connections to a semiconductor or metal layer through an overlying non-conducting layer, such as an oxide layer. In order to produce contact holes, a layer of photoresist is deposited on the wafer surface. The photoresist is exposed to ultraviolet radiation, hardened and developed in order to form a “mask” over the wafer, with openings at the locations of the contact holes. Then the wafer is transferred to an etch station to form the contact holes through the non-conducting layer down to the semiconductor layer. The photoresist mask is then removed, and the contact holes are filled with metal. A similar process is used in producing trenches or vias in the wafer surface.
In order to ensure consistent device performance, the depth, width and bottom surface cleanliness of contact openings must be carefully controlled. (In the context of the present patent application and in the claims, the term “contact openings” refers to all structures of the type described above, including both contact holes, vias and trenches.) Deviations in the dimensions of contact openings can lead to variations in the contact resistance. If these variations are too large, they impact on device performance and can lead to loss of process yield. The manufacturing process must therefore be carefully monitored and controlled, in order to detect deviations in formation of contact openings as soon as they occur and to take corrective action to avoid the loss of costly wafers in process.
It is known in the art to use a scanning electron microscope (SEM) to inspect contact holes. The principles of the SEM and its use in microanalysis of semiconductor device structures are described, for example, by Yacobi et al., in Chapter 2 of Microanalysis of Solids (Plenum Press, New York, 1994), which is incorporated herein by reference. Because the contact holes are typically much deeper than they are wide, a special high aspect ratio (HAR) imaging mode is used. Open holes, which reach down through the dielectric layer to the semiconductor below, appear bright in the image, while closed holes, which do not fully expose the semiconductor layer, are dim.
HAR techniques using a SEM are time-consuming and costly to implement. They are also not capable of distinguishing between different types of blockages that can cause contact holes to be closed (for example, under-etching of the holes, as opposed to deposition of residues in the bottoms of the holes). Furthermore, HAR imaging techniques can generally be used only after the photoresist mask has been cleaned from the wafer surface. Consequently, there is no possibility of continuing the etching process if it is discovered upon inspection that the contact holes have been underetched.
An alternative method for contact hole inspection is described by Yamada et al., in “An In-Line Process Monitoring Method Using Electron Beam Induced Substrate Current,” in Microelectronics-Reliability 41:3 (March 2001), pages 455–459, which is incorporated herein by reference. The compensation current in an electron beam system, also known as the specimen